PROPOSAL FOR TUTORAL(90 mins)
Novel methods for Area, Speed and Power optimization using HLS for FPGA prototyping
High Level Synthesis (HLS) is gaining the attention of the design community as a methodology for ensuring
continued verification during the design cycle. This also allows the designers to describe the design
behaviors at higher abstraction levels. HLS tools include Vivado HLS, MATLAB HDL coder, and a few other tools
which are available in the open source community. They are typically used by digital designers and architects
to design and deploy algorithms that target varied applications in aerospace, communications, image
processing, deep learning, and neural networks, among others. HLS tools reduce code complexity by
approximately 7–10 times, thereby allowing behavioral IP reuse across projects and enabling verification teams
to use high-abstraction-level modeling techniques, such as transaction-level modeling. In addition, a majority
of current systems on chip have embedded processors. More software elements are involved in the design process
due to the co-existence of microprocessors, digital signal processors (DSPs), memories, and customized logic
on a single chip. Hence, an automated HLS process allows designers and architects to experiment with different
hardware–software boundaries and explore various area, power, and performance tradeoffs from a single common
Due to acceleration they offer and early(pre-silicon) enablement of SW teams, FPGAs and Emulation systems are also playing an important role in modern design flows. Moreover, since they are an expensive and precious resource for any organization, it is important to make them to most optimal use in terms of area and speed at which the designs run on them.
For hand-coded RTL designs, there exist numerous design guidelines and methods which allow designers to have optimized FPGA implementations of their designs but very few exist for HLS tools. Even if they do, they are too much dependent on the tool and application design and hence not generic.
Through this tutorial, we will discuss some of the generic methodologies which can help digital designers and architects achieve area, speed and power budgets for their respective designs.
We hope the design community(Conference attendees) especially digital designers would greatly benefit from this tutorial irrespective of the application areas they are working in.
We would be covering two Methodologies broadly as part of the tutorial:
- ASBWIDN (Application Specific Bit Width for Intermediate Data Nodes)
- MDISTE (Multiple DUTs in Single Testbench Environment)
Our benchmarking results show an improvement of 20-50% in area , speed and power dissipation depending on the design and tool against implementations available in literature and also against those available as reference designs by tool vendors(IP cores).
Table of Contents (90 mins):
- 10 min : Basic Introduction to HLS flows and optimization methods already available by tool vendors
- 10 min : FPGA prototyping and Emulation needs for SoCs and their challenges
- 20 min: Methodology 1 : ASBWIDN (Application Specific Bit Width for Intermediate Data Nodes)
- 20 min : Methodology 2 : MDISTE (Multiple DUTs in Single Testbench Environment)
- 20 min : Results achieved for these methodologies on different application designs(Case Studies)
- 10 min: Q&A, brainstorming and other user experiences with HLS tools and Hand-coded RTL optimizations
Patents , Publications and Conference Presentations(In the area of the topic):
- Sikka, Prateek, Abhijit R. Asati, and Chandra Shekhar. "High‐speed and area‐efficient Sobel edge detector on field‐programmable gate array for artificial intelligence and machine learning applications." Computational Intelligence Wiley Online Library (2020).
- Sikka, Prateek, Abhijit Asati, Chandra Shekhar “Method of High-Level Synthesis in Integrated Circuit Design using application specific bit widths” India Patent Application No. 201911028124
- Sikka, Prateek. "Method and system for emulation of multiple electronic designs in a single testbench environment." U.S. Patent Application No. 10/162,915.
- Sikka, Prateek. "Method for enabling CPU-JTAG debugger connection or improving its performance for multi-clock designs running on FPGA or Emulation systems." U.S. Patent Application No. 15/414,107.
- Sikka, Prateek. "Method for improving runtime performance of multi-clock designs on FPGA and Emulation systems using iterative pipelining." U.S. Patent Application No. 15/414,129.
- Sikka, Prateek, Rajesh Chopra, and Manoj Yadav. "Synthesizable DLL on system-on-chip." U.S. Patent No. 8,451,035. 28 May 2013.
- Pandit, Sujay, and Prateek Sikka. "Design and Implementation of Power Optimized Dual Core and Single Core DLX Processor on FPGA." 2018 9th International Conference on Computing, Communication and Networking Technologies (ICCCNT). IEEE, 2018.
- Garg, Sasha, Niharika Agrawal, S. J. Darak, and Prateek Sikka. "Spectral coexistence of candidate waveforms and DME in air-to-ground communications: Analysis via hardware software co-design on Zynq SoC." 2017 IEEE/AIAA 36th Digital Avionics Systems Conference (DASC), pp. 1-6. IEEE, 2017.
- Sikka, Prateek. “Innovative method for better utilization of emulation hardware/FPGA resources” 2016 International Conference on Integrated Circuits and Microsystems (ICICM). IEEE, 2016
- Invited Tutorial : Sikka, Prateek. “ Design and Verification challenges for complex SoCs”. 2019 Springer 2nd International Conference on VLSI, Communication and Signal Processing., 2019 . MNNIT Allahabad.
Prateek Sikka, Principal Emulation Engineer
NXP Semiconductors, Plot No. 2&3, Sector 16 A, Film City, Noida-201301, Uttar Pradesh, India
Telephone No.: +919810762631
Fax No.: +911203955199
Email address: Prateek.email@example.com
Google Scholar Profile
aPrateek Sikka: Principal Emulation Engineer, NXP Semiconductors, Noida, Uttar Pradesh
Tel. No.: +919810762631.
Email : Prateek.firstname.lastname@example.org (SPEAKER)
bProf. Abhijit R Asati: Associate Professor, Electrical and Electronics Engineering
Department, Birla Institute of
Technology and Science, Vidya Vihar Campus, Pilani, Rajasthan, India.
cProf. Chandra Shekhar: Sr. Professor Emeritus, Electrical and Electronics Engineering
Department, Birla Institute of Technology and Science, Vidya Vihar Campus, Pilani, Rajasthan, India.